Modern VLSI Layout Design 책 출판

This book focuses on the VLSI physical design process including simple gate design, mask design, and design verification process. A successful CMOS VLSI design engineer has knowledge in the areas of device operations, circuit design, layout, and simulation. Students learning CMOS IC design should be trained at a fundamental level in these areas. As transistor feature sizes move towards nanoscale dimension, layouts must now be thoroughly considered in the design process because matching, parasitic effects, and leakage power become the limiting factors in many precision and high speed applications. This book evolved from the lecture and Lab notes used since 2000 for teaching the VLSI design class at Northeastern University (EECE4525: VLSI System Design Laboratory) taken by undergraduate students. This book assumes that the readers have a basic understanding of Boolean algebra and fundamental concepts of electrons and holes. At Northeastern University, the VLSI lab class is taken concurrently with the VLSI lecture class (EECE4524). Most of chapters have a lab at the end of the chapter. The Labs have been designed so that students can exercise the concepts they learn in the lecture class using MyCAD. This book has been written as a Lab textbook for undergraduate VLSI supplementary calss for one semester.

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